All Nexus TCODES follow a common message format. An example of a Nexus message, program trace with indirect branch shown inTable 11.2, consists of the TCODE = 4 followed by a message-specific number of packets of differing types. Complete descriptions ofall the message types and their options are given in the Nexus specification.TCODES can be either public (defined in the Nexus standard) or user-defined. Public TCODES defined in the Nexus standard (IEEE-ISTO 5001-2003) include a range of trace options aswell as other Nexus operations. Only a subset of the total available messages must be implemented in a given system. The minimum required messages for an implementation are given in Table 11.3.
Nexus TCODEs can be classified into six different types, which are described in detail in the Nexus specification. Table 11.4 provides asummary of the packet fields that are used for different TCODES. Different TCODE classes include the following: 1. Status indicates status information messages from the target. This group includes register reads and core-specific or watchpoint/breakpoint status, errormessages, and so on (TCODEs 0-2, 8, 15). 2. General register read/write is a group of commands that allow memory-mapped reads and writes between tools and Nexus recommended registers (NRR) or other registers in a Nexus-defined memory map. Amongother general applications,
3. Program trace is a range of trace options that rely on Nexus-defined branch trace schemas, which limit instruction trace todiscontinuities (branches, conditional jumps, interrupts, etc.) and their relative distance from the last trace. By mapping these valuesto an assembled program, debuggers can interpolate branch locationsalign trace, which is useful in correlating execution over multiple cores (TCODEs 3, 4, 9-12, 27-33).Nexus also defines a standard set of debug-related on-chip registers, which facilitate the identification and interface to different cores and sub-systems and to multicore control and debug operations. A standard register set allows simpler integration and control of the instrumentations with embedded debuggers and related tools.
Nexus defines a number of recommended registers, which facilitate the integrationNexus defines and assigns register maps to 63recommended registers, which are accessed by TCODE operations. Different instances of the same register can be associated withdifferent cores by a source field value that can be transmitted as part of each output message. NRRs may contain recommendedfields, specifying controlOptionally, the two BWC registers may be combined with the two data trace attri-bute registers so that a total of two registers may be simultaneously active; that is, two BWC registers, two data trace attribute registers, or one BWCregister and one data trace attribute register.
Most processor debug environments can be adapted to be Nexus-compliant by adding a Nexus wrapper layer around the existing debugblocks. The value of Nexus for processor debug is that it allows a consistent environment for different processor types to beintegrated using a consistent methodology.Nexus defines a method of trace compression that takes advantage of the propertiesTo make efficient use of memory resources during execution trace, Nexus uses a processor instruction compression technique calledbranch trace messaging, which reduces the trace memory required by focusing, capturing only a full trace on instructionflow discontinuities (typically branches).
Because branches and conditional operations typically constitute a small percentage of an overall instruction execution, this can greatly expand the trace RAM utilization. There are other conditions from which trace information can be tightly integrated with debugger software tool chains to allow correlate analysis of the source code. Nexus also supports relative addressing to reduce the number of required address bits transmitted for normal messages. Certain initialization and exception cases (defined within the standard) will cause normal trace messages to be "upgraded" to sync-type messages in which the entire address is transmitted.
Execution trace can be compressed and later expanded for integration with code debugger tools. This feature allows debug blocks storing instruction trace to leverage assumptions in instruction flow in order to conserve trace bandwidth and increase the number ofinstructions that can be stored in trace buffers or exported in real time.
Even with compression, the time needed for trace export can be significant when relying only on JTAG TDO to transmit data. This problem increases proportionally for multicore designs, where each processor and other block has its own debug information. Improving trace interface throughput is a primary reason for implementing
All Nexus TCODES follow a common message format. An example of a Nexus message, program trace with indirect branch shown inTable 11.2, consists of the TCODE = 4 followed by a message-specific number of packets of differing types. Complete descriptions ofall the message types and their options are given in the Nexus specification.TCODES can be either public (defined in the Nexus standard) or user-defined. Public TCODES defined in the Nexus standard (IEEE-ISTO 5001-2003) include a range of trace options aswell as other Nexus operations. Only a subset of the total available messages must be implemented in a given system. The minimum required messages for an implementation are given in Table 11.3.
Nexus TCODEs can be classified into six different types, which are described in detail in the Nexus specification. Table 11.4 provides asummary of the packet fields that are used for different TCODES. Different TCODE classes include the following: 1. Status indicates status information messages from the target. This group includes register reads and core-specific or watchpoint/breakpoint status, errormessages, and so on (TCODEs 0-2, 8, 15). 2. General register read/write is a group of commands that allow memory-mapped reads and writes between tools and Nexus recommended registers (NRR) or other registers in a Nexus-defined memory map. Amongother general applications,
3. Program trace is a range of trace options that rely on Nexus-defined branch trace schemas, which limit instruction trace todiscontinuities (branches, conditional jumps, interrupts, etc.) and their relative distance from the last trace. By mapping these valuesto an assembled program, debuggers can interpolate branch locationsalign trace, which is useful in correlating execution over multiple cores (TCODEs 3, 4, 9-12, 27-33).Nexus also defines a standard set of debug-related on-chip registers, which facilitate the identification and interface to different cores and sub-systems and to multicore control and debug operations. A standard register set allows simpler integration and control of the instrumentations with embedded debuggers and related tools.
Nexus defines a number of recommended registers, which facilitate the integrationNexus defines and assigns register maps to 63recommended registers, which are accessed by TCODE operations. Different instances of the same register can be associated withdifferent cores by a source field value that can be transmitted as part of each output message. NRRs may contain recommendedfields, specifying controlOptionally, the two BWC registers may be combined with the two data trace attri-bute registers so that a total of two registers may be simultaneously active; that is, two BWC registers, two data trace attribute registers, or one BWCregister and one data trace attribute register.
Most processor debug environments can be adapted to be Nexus-compliant by adding a Nexus wrapper layer around the existing debugblocks. The value of Nexus for processor debug is that it allows a consistent environment for different processor types to beintegrated using a consistent methodology.Nexus defines a method of trace compression that takes advantage of the propertiesTo make efficient use of memory resources during execution trace, Nexus uses a processor instruction compression technique calledbranch trace messaging, which reduces the trace memory required by focusing, capturing only a full trace on instructionflow discontinuities (typically branches).
Because branches and conditional operations typically constitute a small percentage of an overall instruction execution, this can greatly expand the trace RAM utilization. There are other conditions from which trace information can be tightly integrated with debugger software tool chains to allow correlate analysis of the source code. Nexus also supports relative addressing to reduce the number of required address bits transmitted for normal messages. Certain initialization and exception cases (defined within the standard) will cause normal trace messages to be "upgraded" to sync-type messages in which the entire address is transmitted.
Execution trace can be compressed and later expanded for integration with code debugger tools. This feature allows debug blocks storing instruction trace to leverage assumptions in instruction flow in order to conserve trace bandwidth and increase the number ofinstructions that can be stored in trace buffers or exported in real time.
Even with compression, the time needed for trace export can be significant when relying only on JTAG TDO to transmit data. This problem increases proportionally for multicore designs, where each processor and other block has its own debug information. Improving trace interface throughput is a primary reason for implementing
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